#define SYS_TMM_SERDES_MAX_NUM 100
#define SYS_TMM_SERDES_PARAM_NONE 0xff
#define SYS_TMM_SERDES_REF_CLK_FREQ 15625
#define SYS_TMM_SERDES_FW_LOAD_CHKSUM 0

enum sys_tmm_serdes_datarate_level_s
{
    SYS_TMM_SERDES_DATARATE_LEVEL_0_TO_2,
    SYS_TMM_SERDES_DATARATE_LEVEL_2_TO_4,
    SYS_TMM_SERDES_DATARATE_LEVEL_4_TO_6,
    SYS_TMM_SERDES_DATARATE_LEVEL_6_TO_12,
    SYS_TMM_SERDES_DATARATE_LEVEL_12_TO_16,
    SYS_TMM_SERDES_DATARATE_LEVEL_16_TO_27,
    SYS_TMM_SERDES_DATARATE_LEVEL_27_TO_30,
    SYS_TMM_SERDES_DATARATE_LEVEL_30_TO_40,
    SYS_TMM_SERDES_DATARATE_LEVEL_40_TO_54,
    SYS_TMM_SERDES_DATARATE_LEVEL_54_TO_58,
    SYS_TMM_SERDES_MAX_DATARATE_LEVEL
};
typedef enum sys_tmm_serdes_datarate_level_s sys_tmm_serdes_datarate_level_t;

enum sys_tmm_serdes_datarate_val_s
{
    SYS_TMM_SERDES_DATARATE_VAL_NRZ_1 = 7,
    SYS_TMM_SERDES_DATARATE_VAL_NRZ_3 = 12,
    SYS_TMM_SERDES_DATARATE_VAL_NRZ_5 = 13,
    SYS_TMM_SERDES_DATARATE_VAL_NRZ_10 = 1,
    SYS_TMM_SERDES_DATARATE_VAL_NRZ_16 = 11,
    SYS_TMM_SERDES_DATARATE_VAL_NRZ_25 = 3,
    SYS_TMM_SERDES_DATARATE_VAL_NRZ_28 = 5,
    SYS_TMM_SERDES_DATARATE_VAL_PAM4_37 = 6,
    SYS_TMM_SERDES_DATARATE_VAL_PAM4_53 = 9,
    SYS_TMM_SERDES_DATARATE_VAL_PAM4_56 = 10
};
typedef enum sys_tmm_serdes_datarate_val_s sys_tmm_serdes_datarate_val_t;

enum sys_tmm_serdes_reset_type_e
{
    SYS_TMM_SERDES_LOGIC_RESET,
    SYS_TMM_SERDES_SOFT_RESET,
    SYS_TMM_SERDES_REGISTER_RESET,
    SYS_TMM_SERDES_CPU_RESET
};
typedef enum sys_tmm_serdes_reset_type_e sys_tmm_serdes_reset_type_t;

enum sys_tmm_serdes_chip_reset_val_e
{
    SYS_TMM_SERDES_CHIP_SOFT_RESET_VAL = 0x888,
    SYS_TMM_SERDES_CHIP_LOGIC_RESET_VAL = 0x777,
    SYS_TMM_SERDES_CHIP_CPU_RESET_VAL = 0xAAA,
    SYS_TMM_SERDES_CHIP_REG_RESET_VAL = 0x999,     
};
typedef enum sys_tmm_serdes_chip_reset_val_e sys_tmm_serdes_chip_reset_val_t;

enum sys_tmm_serdes_nrz_sub_rate_s
{
    SYS_TMM_SERDES_NRZ_SUB_DATA_FLASE,
	SYS_TMM_SERDES_NRZ_SUB_DATA_TRUE,
    SYS_TMM_SERDES_NRZ_SUB_DATA_NULL
};
typedef enum sys_tmm_serdes_nrz_sub_rate_s  sys_tmm_serdes_nrz_sub_rate_t;

enum sys_tmm_serdes_prbs_mode_s
{
    SYS_TMM_SERDES_PRBS_MODE_9,
    SYS_TMM_SERDES_PRBS_MODE_13,
    SYS_TMM_SERDES_PRBS_MODE_15,
    SYS_TMM_SERDES_PRBS_MODE_23,
    SYS_TMM_SERDES_PRBS_MODE_31,
    SYS_TMM_SERDES_PRBS_MODE_MAX
};
typedef enum sys_tmm_serdes_prbs_mode_s ssys_tmm_serdes_prbs_mode_t;

enum sys_tmm_serdes_rx_or_tx_s
{
    SYS_TMM_SERDES_RX,
    SYS_TMM_SERDES_TX
};
typedef enum sys_tmm_serdes_rx_or_tx_s sys_tmm_serdes_rx_or_tx_t;

enum sys_tmm_serdes_glb_info_type_s
{
    SYS_TMM_SERDES_GLB_DATA_RATE,
    SYS_TMM_SERDES_GLB_MD_MODE, /*Modulation Mode : PAM4 or NZR*/
    SYS_TMM_SERDES_GLB_TX_POL,
    SYS_TMM_SERDES_GLB_RX_POL,
    SYS_TMM_SERDES_GLB_BIT_WIDTH,
    SYS_TMM_SERDES_GLB_RATE_DIV,
    SYS_TMM_SERDES_GLB_OVCLK_SPEED,
    SYS_TMM_SERDES_GLB_OPTICAL_MODE,
    SYS_TMM_SERDES_GLB_FEC_TYPE,
    SYS_TMM_SERDES_GLB_INFO_MAX
};
typedef enum sys_tmm_serdes_glb_info_type_s sys_tmm_serdes_glb_info_type_t;

enum sys_tmm_serdes_bit_width_s
{
    SYS_TMM_SERDES_BW_NULL       = 0,    
    SYS_TMM_SERDES_BW_20BITS = 3,     /*CpuMac, Use 20T clock*/
    SYS_TMM_SERDES_BW_32BITS = 4,     /*NRZ*/
    SYS_TMM_SERDES_BW_64BITS = 5,     /*PAM4*/
    SYS_TMM_SERDES_BW_MAX
};
typedef enum sys_tmm_serdes_bit_width_s sys_tmm_serdes_bit_width_t;

enum sys_tmm_serdes_rate_div_s
{
    SYS_TMM_SERDES_RATE_DIV_NULL     = 0,    
    SYS_TMM_SERDES_RATE_DIV_FULL,  
    SYS_TMM_SERDES_RATE_DIV_HALF, 
    SYS_TMM_SERDES_RATE_DIV_QUAD,    
    SYS_TMM_SERDES_RATE_DIV_EIGHTH,
    SYS_TMM_SERDES_RATE_DIV_HEXL
};
typedef enum sys_tmm_serdes_rate_div_s sys_tmm_serdes_rate_div_t;

struct sys_tmm_serdes_fw_load_info_s
{
    uint16 load_info_code;
    uint16 magic_word;
    uint16 crc_code;
    uint32 hash_code;
};
typedef struct sys_tmm_serdes_fw_load_info_s sys_tmm_serdes_fw_load_info_t;

struct sys_tmm_serdes_info_s
{
    uint8 serdes_mode;
    uint8 data_rate;
    uint8 pam4_or_nrz;
    uint8 rx_polarity;
    uint8 tx_polarity;
};
typedef struct sys_tmm_serdes_info_s  sys_tmm_serdes_info_t;

struct sys_tmm_serdes_datapath_config_param_s
{
    uint8 gray_code;
    uint8 pre_code;
    uint8 msblsb;
};
typedef struct sys_tmm_serdes_datapath_config_param_s sys_tmm_serdes_datapath_config_param_t;

struct sys_tmm_serdes_serdes_config_param_s
{
    uint8 serdes_id;
    uint8 pam4_or_nrz;
    uint8 datarate_val;
    uint8 nrz_sub_rate;
    uint8 prbs_pattern;
    uint8 baud_rate_ratio;
    uint8 rx_input_mode;
    uint8 datarate_set_mode;/*0:by firmware 1:by set_pll*/
    sys_tmm_serdes_datapath_config_param_t tx;
    sys_tmm_serdes_datapath_config_param_t rx;
};
typedef struct sys_tmm_serdes_serdes_config_param_s sys_tmm_serdes_serdes_config_param_t;

struct sys_tmm_serdes_fw_config_param_s
{
    uint8 serdes_id;
    uint8 data_rate; /*ctc_chip_serdes_mode_t*/
    uint8 tx_idx;
    uint8 link_train;
    uint8 optical_mode;
    uint8 ovclk_speed;
    uint8 lt_nrz_init;
};
typedef struct sys_tmm_serdes_fw_config_param_s sys_tmm_serdes_fw_config_param_t;

enum sys_tmm_serdes_pam4_or_nrz_mode_s
{
    SYS_TMM_SERDES_PAM4_MODE,
    SYS_TMM_SERDES_NRZ_MODE
};
typedef enum sys_tmm_serdes_pam4_or_nrz_mode_s sys_tmm_serdes_pam4_or_nrz_mode_t;

enum sys_tmm_serdes_link_train_type_s
{
    SYS_TMM_SERDES_LINK_TRAIN_TYPE_DISABLE,
    SYS_TMM_SERDES_LINK_TRAIN_TYPE_ENABLE,
    SYS_TMM_SERDES_LINK_TRAIN_TYPE_PRBS
};
typedef enum sys_tmm_serdes_link_train_type_s sys_tmm_serdes_link_train_type_t;

enum sys_tmm_serdes_datapath_prop_e
{
    SYS_TMM_SERDES_DATAPATH_PROP_GC,//Gray Code
    SYS_TMM_SERDES_DATAPATH_PROP_PC,//Precode
    SYS_TMM_SERDES_DATAPATH_PROP_MSBLSB,//MSBLSB
    SYS_TMM_SERDES_DATAPATH_PROP_MAX
};
typedef enum sys_tmm_serdes_datapath_prop_e sys_tmm_serdes_datapath_prop_t;

struct  sys_tmm_serdes_datapath_prop_cfg_s
{
    uint8 dir;                                         /**0:rx, 1:tx */
    uint8 serdes_id;                                   /**serdes id */
    uint16 mode_val;                                   /**0:disable, 1:enable */
};
typedef struct sys_tmm_serdes_datapath_prop_cfg_s sys_tmm_serdes_datapath_prop_cfg_t;

enum sys_tmm_serdes_pll_set_mode_s
{
	SYS_TMM_SERDES_PLL_SET_MODE_BY_PLL_N, 
	SYS_TMM_SERDES_PLL_SET_MODE_BY_DATA_RATE_FRE
};
typedef enum sys_tmm_serdes_pll_set_mode_s sys_tmm_serdes_pll_set_mode_t;

enum  sys_tmm_serdes_wr_mode_s
{
    SYS_TMM_SERDES_WR_MODE_UCAST = 0,     /*Unicast mode*/
    SYS_TMM_SERDES_WR_MODE_BCAST          /*BroadCast mode*/
};
typedef enum sys_tmm_serdes_wr_mode_s sys_tmm_serdes_wr_mode_t;

int32
sys_tmm_serdes_get_signal_detect(uint8 lchip, uint8 physic_serdes_id, uint8* p_is_detect, uint8* p_raw_sigdet);

int32 
sys_tmm_serdes_set_glb_info(uint8 lchip, uint8 physic_serdes_id, sys_tmm_serdes_glb_info_type_t type, uint8 value);


